Build instructions

Source code

The source code for the reference designs is managed on this Github repository:

https://github.com/fpgadeveloper/fpga-drive-aximm-pcie

To get the code, you can follow the link and use the Download ZIP option, or you can clone it using this command:

git clone https://github.com/fpgadeveloper/fpga-drive-aximm-pcie.git

License requirements

Some of the designs in this repository target dev boards for which a license is required to generate a bitstream. Others can be built with the Vivado ML Standard Edition without a license. The table of target designs in the following section contains a column specifying which designs require a license, and which can be built without a license.

Target designs

This repo contains several designs that target the various supported development boards and their FMC connectors. The table below lists the target design name, the M2 ports supported by the design and the FMC connector on which to connect the mezzanine card.

FPGA designs

Target board	Target design	M.2 Slot 1 PCIe Lanes	M.2 Slot 2 PCIe Lanes	FMC Slot	Vivado Edition
KC705	`kc705_hpc`	X4	-	HPC	Enterprise
KC705	`kc705_lpc`	X1	-	LPC	Enterprise
KCU105	`kcu105_hpc`	X4	X4	HPC	Enterprise
KCU105	`kcu105_lpc`	X1	-	LPC	Enterprise
VC707	`vc707_hpc1`	X4	-	HPC1	Enterprise
VC707	`vc707_hpc2`	X4	-	HPC2	Enterprise
VC709	`vc709_hpc`	X4	-	HPC	Enterprise
VCU118	`vcu118`	X4	X4	FMCP	Enterprise

Zynq-7000 designs

Target board	Target design	M.2 Slot 1 PCIe Lanes	M.2 Slot 2 PCIe Lanes	FMC Slot	Vivado Edition
PicoZed 7015	`pz_7015`	X1	-	LPC	Standard 🆓
PicoZed 7030	`pz_7030`	X1	-	LPC	Standard 🆓
ZC706	`zc706_hpc`	X4	-	HPC	Enterprise
ZC706	`zc706_lpc`	X1	-	LPC	Enterprise

Zynq UltraScale+ designs

Target board	Target design	M.2 Slot 1 PCIe Lanes	M.2 Slot 2 PCIe Lanes	FMC Slot	Vivado Edition
UltraZed-EV Carrier	`uzev`	X4	X4	HPC	Standard 🆓
ZCU104	`zcu104`	X1	-	LPC	Standard 🆓
ZCU106	`zcu106_hpc0`	X4	X4	HPC0	Standard 🆓
ZCU106	`zcu106_hpc1`	X1	-	HPC1	Standard 🆓
ZCU111	`zcu111`	X4	X4	FMCP	Enterprise
ZCU208	`zcu208`	X4	X4	FMCP	Enterprise
ZCU216	`zcu216`	X4	X4	FMCP	Enterprise

Versal designs

Target board	Target design	M.2 Slot 1 PCIe Lanes	M.2 Slot 2 PCIe Lanes	FMC Slot	Vivado Edition
VCK190	`vck190_fmcp1`	X4	X4	FMCP1	Enterprise
VCK190	`vck190_fmcp2`	X4	X4	FMCP2	Enterprise
VHK158	`vhk158`	X4	-	FMCP	Enterprise
VMK180	`vmk180_fmcp1`	X4	X4	FMCP1	Enterprise
VMK180	`vmk180_fmcp2`	X4	X4	FMCP2	Enterprise
VEK280	`vek280`	X4	X4	FMCP	Enterprise
VPK120	`vpk120`	X4	-	FMCP	Enterprise
VPK180	`vpk180`	X4	-	FMCP	Enterprise

Notes:

The Vivado Edition column indicates which designs are supported by the Vivado Standard Edition, the FREE edition which can be used without a license. Vivado Enterprise Edition requires a license however a 30-day evaluation license is available from the AMD Xilinx Licensing site.

Windows users

Windows users will be able to build the Vivado projects and compile the standalone applications, however Linux is required to build the PetaLinux projects.

Tip

If you wish to build the PetaLinux projects, we recommend that you build the entire project (including the Vivado project) on a machine (either physical or virtual) running one of the supported Linux distributions.

Build Vivado project in Windows

Download the repo as a zip file and extract the files to a directory on your hard drive –OR– clone the repo to your hard drive
Open Windows Explorer, browse to the repo files on your hard drive.
In the Vivado directory, double click on the build-vivado.bat batch file. You will be prompted to select a target design to build. You will find the project in the folder Vivado/<target>.
Run Vivado and open the project that was just created.
Click Generate bitstream.
When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick Include bitstream and use the default name and location for the XSA file.

Build Vitis workspace in Windows

Before running these steps, you must first build and export the Vivado project as described above.

Return to Windows Explorer and browse to the Vitis directory in the repo.
Double click the build-vitis.bat batch file. You will be prompted to select a target design. A Vitis workspace with hardware platform and software application will be created for the selected target design. You will find the Vitis workspace in the folder Vitis/<target>_workspace.

Linux users

These projects can be built using a machine (either physical or virtual) with one of the supported Linux distributions.

Tip

The build steps can be completed in the order shown below, or you can go directly to the build PetaLinux instructions below to build the Vivado and PetaLinux projects with a single command.

Build Vivado project in Linux

Open a command terminal and launch the setup script for Vivado:
```
source <path-to-vivado-install>/2024.1/settings64.sh
```

Clone the Git repository and cd into the Vivado folder of the repo:

git clone https://github.com/fpgadeveloper/fpga-drive-aximm-pcie.git
cd fpga-drive-aximm-pcie/Vivado

Run make to create the Vivado project for the target board. You must replace <target> with a valid target (alternatively, skip to step 5):
```
make project TARGET=<target>
```
Valid target labels are: kc705_hpc, kc705_lpc, kcu105_hpc, kcu105_lpc, pz_7015, pz_7030, uzev, vc707_hpc1, vc707_hpc2, vc709_hpc, vck190_fmcp1, vck190_fmcp2, vhk158, vmk180_fmcp1, vmk180_fmcp2, vek280, vpk120, vpk180, vcu118, zc706_hpc, zc706_lpc, zcu104, zcu106_hpc0, zcu106_hpc1, zcu111, zcu208, zcu216. That will create the Vivado project and block design without generating a bitstream or exporting to XSA.
Open the generated project in the Vivado GUI and click Generate Bitstream. Once the build is complete, select File->Export->Export Hardware and be sure to tick Include bitstream and use the default name and location for the XSA file.
Alternatively, you can create the Vivado project, generate the bitstream and export to XSA (steps 3 and 4), all from a single command:
```
make xsa TARGET=<target>
```

Build Vitis workspace in Linux

The following steps are required if you wish to build and run the standalone application. You can skip to the following section if you instead want to use PetaLinux. You are not required to have built the Vivado design before following these steps, as the Makefile triggers the Vivado build for the corresponding design if it has not already been done.

Launch the setup scripts for Vitis:

source <path-to-vitis-install>/2024.1/settings64.sh

To build the Vitis workspace, cd to the Vitis directory in the repo, then run make to create the Vitis workspace and compile the standalone application:
```
cd fpga-drive-aximm-pcie/Vitis
make workspace TARGET=<target>
```
Valid target labels for the workspaces are: kc705_hpc, kc705_lpc, kcu105_hpc, kcu105_lpc, pz_7015, pz_7030, uzev, vc707_hpc1, vc707_hpc2, vc709_hpc, vck190_fmcp1, vck190_fmcp2, vhk158, vmk180_fmcp1, vmk180_fmcp2, vek280, vpk120, vpk180, vcu118, zc706_hpc, zc706_lpc, zcu104, zcu106_hpc0, zcu106_hpc1, zcu111, zcu208, zcu216. You will find the Vitis workspace in the folder Vitis/<target>_workspace.

Build PetaLinux project in Linux

These steps will build the PetaLinux project for the target design. You are not required to have built the Vivado design before following these steps, as the Makefile triggers the Vivado build for the corresponding design if it has not already been done.

Launch the setup script for Vivado (only if you skipped the Vivado build steps above):
```
source <path-to-vivado-install>/2024.1/settings64.sh
```
Launch PetaLinux by sourcing the settings.sh bash script, eg:
```
source <path-to-petalinux-install>/2024.1/settings.sh
```
Build the PetaLinux project for your specific target platform by running the following command, replacing <target> with a valid value from below:
```
cd PetaLinux
make petalinux TARGET=<target>
```
Valid target labels for PetaLinux projects are: pz_7015, pz_7030, uzev, vck190_fmcp1, vck190_fmcp2, vhk158, vmk180_fmcp1, vmk180_fmcp2, vek280, vpk120, vpk180, zc706_hpc, zc706_lpc, zcu104, zcu106_hpc0, zcu106_hpc1, zcu111, zcu208, zcu216. Note that if you skipped the Vivado build steps above, the Makefile will first generate and build the Vivado project, and then build the PetaLinux project.

PetaLinux offline build

If you need to build the PetaLinux projects offline (without an internet connection), you can follow these instructions.

Download the sstate-cache artefacts from the Xilinx downloads site (the same page where you downloaded PetaLinux tools). There are four of them:
- aarch64 sstate-cache (for ZynqMP designs)
- arm sstate-cache (for Zynq designs)
- microblaze sstate-cache (for Microblaze designs)
- Downloads (for all designs)

Extract the contents of those files to a single location on your hard drive, for this example we’ll say /home/user/petalinux-sstate. That should leave you with the following directory structure:

/home/user/petalinux-sstate
                          +---  aarch64
                          +---  arm
                          +---  downloads
                          +---  microblaze

Create a text file called offline.txt in the PetaLinux directory of the project repository. The file should contain a single line of text specifying the path where you extracted the sstate-cache files. In this example, the contents of the file would be:
```
/home/user/petalinux-sstate
```
It is important that the file contain only one line and that the path is written with NO TRAILING FORWARD SLASH.

Now when you use make to build the PetaLinux projects, they will be configured for offline build.